1. Field of the Invention
The disclosed embodiments of the present invention relate to data transmission, and more particularly, to a data transmission circuit and a data transmission method using a configurable threshold and a related universal serial bus system.
2. Description of the Prior Art
In a general universal serial bus (USB) system, if a user wants to move data in a memory of a peripheral element to a host via a USB transmission line, an aggregation method is employed to reduce the number of moving operations of the data, so as to lower the utilization of a central processing unit (CPU) of a host and accordingly decrease the loading of the CPU.
In accordance with the conventional aggregation transmission method, it is required to assign a fixed threshold to the memory of the peripheral element. When data volume in the memory reaches the fixed threshold, the peripheral element starts moving data from the memory to the host. Please refer to FIG. 1, which is a schematic diagram illustrating a threshold of a memory 110 and each transmission data. As shown in FIG. 1, when the memory 110 is configured to have a lower threshold, the size of each transmission data (#1˜#N+1) would be smaller (i.e., data volume maintains roughly at the same level of the threshold), and the utilization of the CPU would be higher (i.e., the loading of the CPU is heavier). However, at this moment, the memory 110 may have more buffering capacity to accommodate incoming data. On the other hand, when the memory 110 is configured to have a higher threshold, the size of each transmission data (#1˜#M) would be larger, and the utilization of the CPU would be lower (i.e., the loading of the CPU is lighter). However, at this moment, the buffering capacity of the memory 110 would be relatively insufficient.
To sum up, since there is a conflict between the utilization of the CPU and the buffering capacity of the memory of the peripheral element, a system designer has to take both factors into account and balance the trade-offs. In other words, the conventional design fails to achieve optimized CPU utilization as well as optimized memory buffering capacity.